Covered Free and open source Verilog code coverage analysis tool
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Covered Ranking & Summary

Covered Tags

read generate analyze read verilog file verilog file analysis generate cdd

Covered Description

Free and open source Verilog code coverage analysis tool Covered reads in the Verilog design files and a VCD or LXT formatted dumpfile from a diagnostic run and generates a database file called a Coverage Description Database (CDD) file, using the score command. Covered's score command can alternatively be used to generate a CDD file and a Verilog module for using Covered as a VPI module in a testbench which can obtain coverage information in parallel with simulation. The resulting CDD file can be merged with other CDD files from the same design to create accummulated coverage, using the merge command. Once a CDD file is created, the user can use Covered to generate various human-readable coverage reports in an ASCII format or use Covered's GUI to interactively look at coverage results, using the report command. Additionally, as part of Covered's score command, race condition possibilities are found in the design files and can be either flagged as errors, ignoredor flagged as warnings. By specifying race conditions as errors, Covered can also be used as a race condition checker.Covered currently supports Verilog-1995, Verilog-2001 (with the exception of config blocks currently), and some SystemVerilog constructs. Metrics that are generated include the following:· Line coverage· Toggle coverage· Memory coverage· Combinational logic coverage· FSM state and state-transition coverage· Assertion (functional) coverage What's New in This Release: · Adding support for $random and $urandom system calls to inlined coverage. · Includes all fixes made to the stable 0.7.5 release. · Adding support for $value$plusargs system calls to inlined coverage. · Fixing issue with generated IF statements. · Added user documentation for inlined coverage flow and score options. · Fixing issue with generated code interrupting comma-separated assign statements. · Performed code simplification and performance improvement with the way statements were handled internally. · Removed unnecessary calls to simulation functions when using inlined code coverage (this added a performance penalty). · Improved performance of inlined code generator for sizing generated signals. · Fixed memory indexing issues related to memory coverage. · Added support for static function and static ternary operators for inlined code coverage. · Added code to differentiate functions used statically and not to do the right thing for inlined code coverage accumulation. · Added vcd_diff script which checks the dumpfile output from non-inlined and inlined design files to verify that the inlined code generator does not change the result. This check is now a part of all inlined regression runs. · Made several performance improvements to the VCD file reader. The reader is now 10-20% faster. · Added support for Verilator regressions runs and ported a couple of diagnostics to Verilator format. · Adding check to make sure that a CDD file without inlined mode set that reads a VCD file containing inlined coverage data emits an error to the user and exits gracefully. · Added -inline-comb-depth score option to allow the user to specify a shallower combinational coverage depth to be generated -- improving inlined simulation and coverage performance. · For Verilator runs, inserted pragmas around intermediate combinational logic expression signals to exclude them from being output to VCD files. This improves simulation and coverage performance for Verilator runs (other simulators that have a VPI that automatically remove these signals from generating change callbacks). · Performing code replace of some actual code with pre-calculated intermediate expression values for further simulation performance improvements. · Added "e" option to -inline-metrics which allows event coverage to be turned on/off independently of other combinational logic coverage. This allows further simulation and coverage performance improvements (especially for Verilator runs). · Added optimization that causes code generation to be skipped for assertion files when assertion coverage is not required. · Full regressions now runs cleanly with all code changes.

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