Icarus VerilogVerilog simulation and synthesis tool | |
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Icarus Verilog Ranking & Summary
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- License:
- GPL
- Price:
- FREE
- Publisher Name:
- Stephen Williams
- Publisher web site:
- http://icarus.com/eda/verilog/
- Operating Systems:
- Mac OS X
- File Size:
- 1.1 MB
Icarus Verilog Tags
Icarus Verilog Description
Verilog simulation and synthesis tool Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the ``vvp'' command. For synthesis, the compiler generates netlists in the desired format.The compiler proper is intended to elaborate and parse design descriptions written to the IEEE standard IEEE Std 1364-2001. The standard proper was released towards the middle of the year 2001, though in a rather pricey electronic form.This is a fairly large and complex standard, so it will take some time for it to get there, but that's the goal.NOTE: Icarus Verilog is a work in progress, and since the language standard is not standing still either, it probably always will be.
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